(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a method of fabricating a metal oxide semiconductor field effect transistor (MOSFET), device, featuring two individual salicide formation procedures, one for the gate structures and the another for the source/drain regions.
(2) Description of Prior Art
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices using sub-micron features, has allowed performance increases, as well as reductions in the fabrication costs of the sub-micron devices, to be realized. The use of sub-micron features allow reductions in performance degrading parasitic capacitances to be achieved. In addition micro-miniaturization allows a greater number of smaller semiconductor chips to be obtained from a specific size starting substrate, still offering device densities of larger counterpart semiconductor chips, thus reducing the fabrication cost for a specific semiconductor chip.
MOSFET devices formed using sub-micron ground rules can however result in unwanted phenomena during specific fabrication procedures, such as the processes used to form self-aligned metal silicide (salicide), layers. These phenomena, observed with devices formed with sub-micron features are not present when forming MOSFET devices using larger features. First the narrow width of gate, or word line structures, necessitate the formation of thicker metal silicide regions to satisfy and equal the conductivity or performance objectives realized with wider word lines. A single salicide procedure used to form a desired thick metal silicide on the narrow word lines would also form the same thick metal silicide layer on the source/drain regions. Since the use of micro-miniaturization also features shallower depths, the formation of the thick metal silicide layer on the shallow source/drain region can result in unwanted leakage or shorts as a result of aggressive consumption of the shallow source/drain region. In addition the aggressive salicide formation procedure needed for thick layers on the gate or word line structures, in terms of increased metal thickness as well as increased formation temperature and time, can lead to gate to substrate shorts as a result of stringers, or metal silicide ribbons, forming on an insulator spacer, thus physically and electrically connecting the word line to the source/drain region.
This invention will describe a novel fabrication sequence in which a dual salicide process is used, where a first salicide formation procedure is used for formation of a thick metal silicide layer on the narrow width gate structures, and a second salicide formation procedure is employed to form a thinner metal silicide layer on the shallow depth source/drain regions. This invention will feature protection of the shallow source/drain region, during the first salicide formation procedure, via use of an overlying insulator layer. The same insulator layer is used for definition of insulator spacers, using a protruding portion of the thick metal silicide layer as an etch mask. Prior art, such as Gardner et al, in U.S. Pat. No. 6,100,173, as well as Hause et al, in U.S. Pat. No. 6,156,649, describe double salicide processes, however known of these prior arts describe the novel features described in the present invention, such as a first thick salicide formation on the word line structure with a portion of a salicide region extending over the adjacent insulator layer serving as a mask for definition of the underlying insulator spacers.
It is an object of this invention to fabricate a MOSFET device using a double salicide formation process, with a first salicide procedure used to form a thick metal silicide region on a narrow width, word line structures, while a second salicide process is used to form a thinner metal silicide layer on a shallow source/drain region.
It is another object of this invention to perform the formation of the thick metal silicide layer on a word line structure encased in an insulator layer, and to allow a portion of the thick metal silicide layer to extend, and overlay a portion of the top surface of the adjacent, encasing insulator layer.
It is still another object of this invention to use the extending portion of the thick metal silicide layer as an etch mask for definition of insulator spacers, via an anisotropic RIE procedure performed to the adjacent insulator layer.
In accordance with the present invention a double salicide formation procedure, used to form a thick, first metal silicide layer on a word line of a MOSFET device, and to form a thinner, second metal silicide layer on the source/drain region of the same MOSFET device, is described. After formation of a polysilicon gate, or word line structure, on a thin underlying silicon dioxide gate insulator layer, an insulator layer is deposited and polished back to expose the top surface of the polysilicon gate structure. After deposition of a first metal layer a first thermal procedure is employed to form a thick metal silicide layer on a bottom portion of the polysilicon gate structure via consumption of a top portion of the polysilicon gate structure, with the first thermal procedure also resulting in a thick metal silicide layer extension, located overlaying a top portion of the adjacent, planar insulator layer. After removal of the unreacted portions of the first metal layer, the thick metal silicide extensions are used as an mask to allow an anisotropic RIE procedure to form insulator spacers on the sides of the word line structure, now comprised with a top portion of thick metal silicide, and a bottom portion of unconsumed polysilicon. A second metal layer is then deposited followed by a second thermal procedure, used to form a self-aligned, thinner metal silicide layer on the exposed source/drain regions. This is followed by removal of unreacted portions of the second metal layer.